Lead ASIC/FPGA Verification EngineerEl Segundo, California; Los Angeles, California
At Boeing, we are all innovators on a mission to connect, protect, explore and inspire. From the sea bed to outer space, you’ll learn and grow, contributing to work that shapes the world. Find your future with us.
Boeing Defense Space & Security seeks a Lead Digital ASIC/FPGA Verification Engineer to support the Satellite Capabilities organization and multiple satellite product lines based in El Segundo, CA.
- Utilize high-level architectural documentation along with algorithm description and implement DSP functions for functions such as decimation, interpolation, general filtering, up-down conversion, digital beamforming, and channelization.
- Develop mathematical models in SystemVerilog to verify design implementation and develop and run scripts and Make files.
- Leads analysis of customer and system requirements and development of architectural approaches and detailed specifications for various electronic products.
- Leads development of high-level and detailed designs consistent with requirements and specifications.
- Leads verification of high-level and detailed designs consistent with requirements and specifications.
- Leads reviews of simulation and analysis activity to assure compliance to requirements.
- Identifies, tracks and statuses technical performance measures to measure progress and ensure compliance with requirements.
- Leads activities in support of Supplier Management with make/buy recommendations and other technical services.
- Coordinates engineering support throughout the lifecycle of the product.
- Plans research projects to develop concepts for future product designs to meet projected requirements.
- Works under minimal direction.
This position offers relocation based on candidate eligibility. Basic relocation is available for internal candidates.
Basic Qualifications (Required Skills/Experience):
- This position must meet Export Control compliance requirements, therefore a “US Person” as defined by 22 C.F.R. § 120.15 is required. “US Person” includes US Citizen, lawful permanent resident, refugee, or asylee.
- Bachelor, Master or Doctorate of Science degree from an accredited course of study, in engineering, computer science, mathematics, physics or chemistry.
4 or more years' of experience using object oriented programming (OOP), e.g. Java, Python, Ruby, C++, Objective-C, Visual Basic .NET, Smalltalk, Curl, Delphi, Eiffel, or SystemVerilog with OOP constructs.
- Work experience using Linux or Unix terminal commands.
- Work experience using scripting languages: Make, Perl, Python, shell scripts, etc.
Preferred Qualifications (Desired Skills/Experience):
- 4 or more years of experience in digital ASIC/FPGA verification/simulation.
- 4 or more years of experience with Object Oriented Programming (OOP) and Universal Verification Methodology (UVM): creating UVM drivers, monitors, predictors, and scoreboards.
- Work experience using SystemVerilog and SystemVerilog Assertions (SVA).
- Experience leading review of test/simulation results and analysis to ensure compliance of the design to the requirements specification.
- Experience developing functional coverage models and closing code coverage.
- Experience working in an Agile/iterative development and design process.
- Work experience creating self-checking simulation testbenches from scratch.
- Work experience creating reusable testbench components.
- Work experience writing test/simulation plans, simulation procedures, and results reports.
- Experience identifying, tracking, and providing status of technical performance metrics to measure progress and ensure compliance with requirements.
- Experience leading a team of engineers.
- Bachelor's degree and 12 or more years' experience in digital ASIC/FPGA design and verification, Master's degree with 10 or more years' experience in digital design/verification, or PhD degree with 7 years of experience in digital design verification.
- Experience designing testbenches specifically optimized for hardware emulators (to accelerate simulations).
- Experience using Revision Control Systems: Subversion (SVN), CVS, Git.
- Work experience with HDL design, coding, and debug.
- Experience mentoring junior engineers, (e.g. teaching UVM and other verification concepts).
Typical Education / Experience
Degree and typical experience in engineering classification: Bachelor's and 9 or more years' experience, Master's with 7 or more years' experience or PhD with 4 or more years' experience. Bachelor, Master or Doctorate of Science degree from an accredited course of study, in engineering, computer science, mathematics, physics or chemistry. ABET is the preferred, although not required, accreditation standard.
Boeing is a Drug Free Workplace where post offer applicants and employees are subject to testing for marijuana, cocaine, opioids, amphetamines, PCP, and alcohol when criteria is met as outlined in our policies.
Contingent Upon Program Award
No, this position is not contingent upon program award
Boeing is an Equal Opportunity Employer. Employment decisions are made without regard to race, color, religion, national origin, gender, sexual orientation, gender identity, age, physical or mental disability, genetic factors, military/veteran status or other characteristics protected by law.
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